1. Field of the Invention
The present invention relates to complementary bipolar and MOS integrated circuit semiconductor devices and processes, and more particularly to a semiconductor device with a P- well, and a fabrication method for forming a buried P+ subcollector with a self-aligned reachthrough using a low temperature expitaxial and planarization technique.
2. Description of the Prior Art
U.S. Pat. No. 3,838,440 issued Sep. 24, 1974 to McCaffrey et al entitled A MONOLITHIC MOS/BIPOLAR INTEGRATED CIRCUIT STRUCTURE describes an integrated circuit with a MOS device including an N+ region formed by a combination of epitaxial growth and ion implantation which provides a pocket filled with higher resistivity, lightly doped N type material. Over extended growth and etch back are not shown or discussed in the patent.
The publication FORMATION OF PLANAR n+ POCKETS IN GaAs FOR MIXER DIODE FABRICATION, by James A. Griffin et al, IEEE Transactions on Electron Devices, Vol. Ed-31No. 8, August 1984, pages 1096-1099 describes a technique to produce thick n+ "pockets" of highly conducting epitaxial material on the substrate surface in semi-insulating GaAs bulk material. The pockets are formed by the growth of a liquid-phase epitaxial (LPE) layer into holes which had been etched into the substrate and surface uniformity is obtained by chemo-mechanically polishing the substrate surface.